Reconfigurable acceleration and emerging memory technologies for scalable sensor networks (Delivered in English)
- LecturerDr. Jeffrey Chen (Computer Science PhD graduate, University of California, Irvine, USA)
Host: Yuan-Hao Chang - Time2025-03-28 (Fri.) 10:30 ~ 12:30
- LocationN106 of IIS
Abstract
Battery-powered wireless sensor nodes are one of the fundamental components of IoT-style wide-scale data collection and processing, and are being explored to solve many urgent problems, including industrial equipment maintenance, wildlife monitoring, and natural disaster detection. However, their capabilities are often limited by the power consumption of wireless data transmission, which typically accounts for the majority of a sensor node's power budget. Collecting and transmitting more data requires larger batteries or power harvesters, increasing cost and maintenance overhead. Extreme edge computing attempts to mitigate this issue by offloading some computation to the sensor nodes with the aim of reducing the wireless data transfer requirements. Unfortunately, edge computing on conventional general-purpose processors often ends up consuming more power than it can reduce from wireless transmission, defeating the purpose of edge computing.
This dissertation presents the design and evaluation of three new FPGA-based systems, each of which introduces new approaches to minimizing power consumption, and subsequently cost, of edge sensor nodes. The first system, Eciton, reduces the overhead of power-hungry wireless data transmission by using a low-power FPGA accelerator to filter out uninteresting signals. The second system, Xyloni, builds on the idea of accelerated filtering and addresses the cost and power overhead of random access memory requirements by replacing power-hungry DRAM with dense, low-power non-volatile fabric such as NAND flash memory and Ferroelectric RAM. The final system, Myrmec, minimizes the cost of data movement within the edge sensor node by organizing the accelerator in a SmartNIC configuration. The three systems are evaluated with various real-world scenarios, including predictive maintenance and vision-based wildfire detection, and apply
embedded neural network models of realistic scale to intelligently filter out benign information. The results show that each idea significantly improves cost and power efficiency. The aggregate benefit of all approaches exceeds an order of magnitude improvement in power and cost efficiency compared to the baseline.
This dissertation presents the design and evaluation of three new FPGA-based systems, each of which introduces new approaches to minimizing power consumption, and subsequently cost, of edge sensor nodes. The first system, Eciton, reduces the overhead of power-hungry wireless data transmission by using a low-power FPGA accelerator to filter out uninteresting signals. The second system, Xyloni, builds on the idea of accelerated filtering and addresses the cost and power overhead of random access memory requirements by replacing power-hungry DRAM with dense, low-power non-volatile fabric such as NAND flash memory and Ferroelectric RAM. The final system, Myrmec, minimizes the cost of data movement within the edge sensor node by organizing the accelerator in a SmartNIC configuration. The three systems are evaluated with various real-world scenarios, including predictive maintenance and vision-based wildfire detection, and apply
embedded neural network models of realistic scale to intelligently filter out benign information. The results show that each idea significantly improves cost and power efficiency. The aggregate benefit of all approaches exceeds an order of magnitude improvement in power and cost efficiency compared to the baseline.
BIO
Jeffrey Chen is Computer Science PhD graduate of the University of California, Irvine. He also has a Bachelor of Engineering in Computer Engineering from New York University Abu Dhabi, and a Master of Science in Computer Science from the University of California, Los Angeles. He is a member of the Architectures for Data group at UCI, which emphasizes innovative system architectures for high-performance computing. Jeffrey's personal focus is on low-cost, power-efficient reconfigurable embedded system architectures.